1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the management and control of bus transactions within data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems having bus structures to connect different circuit elements and via which bus transactions, such as reads, writes and control functions take place. As data processing systems become more complex, such as increasingly complex system on-chip integrated circuits, the bus structures used to connect the various functional elements within the circuit have tended to become more complicated and critical in terms of overall system performance. One known type of bus structure uses a unified read and write channel along which serialized bus transactions are passed. Such a unified channel approach has the advantage that the order in which the bus transactions are issued will be the same as the order in which they are received since all of the bus transactions are serialized at issue on the unified channel. However, such an approach suffers from the disadvantage of a limitation in bus bandwidth and an increase in latency since all of the transactions must pass along a single channel.
An alternative approach is to provide the bus structure with separate read buses and write buses along which data can pass in parallel. Such an approach increases the bus bandwidth available and reduces latency.